Altera PCIe not detected due to UEFI0067 Error at boot time

[Altera_Forum]

Hello  

  We are using Altera Arria V GX 5AGXMA7D4F27I3 in a PCIe board developed in house, we have occasionally been experiencing the PCIe board not being detected by the host (Windows); this problem is occasional, so we do not see it all the time and not all all machines. When we have this problem Windows shows the following message when booting up:   "UEFI0067: A PCIe link training failure is observed in PCIe Slot 2 and device link is disabled. A PCIe link failure is observed in the PCIe device identified in the message and device link is disabled. Recommended Response Action Do one of the following: 1) Turn off the input power to the system and turn on again. 2) Update the PCIe device firmware. If the issue persists, contact your service provider."   Altera suggested a work-around by using a soft reset controller in the PCIe IP (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd11192013_905.html), however, we tried this and did not fix the problem.   PS: When we see this problem, the logic inside the board seems to be working as the board LEDs are blinking, so the FPGA logic and clocks are functioning.   Cheers, Chafik

[xytech]

HI Chafik

we are considering similar question recently. my suggestion is , please check the configuration time consumption of FPGA, if it excedd 100ms, the PC might failed to detect the downstream pcie node.

Following info quoted from xinlinx applicaiton note xapp1179, pls refer to pcie spec for more details.

The PCI Express specification states that fundamental reset must remain asserted for at least

100 ms after power becomes valid. It also states that a device must enter the detect state (be

ready for link training) 20 ms after release of the fundamental reset. Therefore, PCI Express

cores must be ready to start link training 120 ms after the power good signal. Due to legacy

reasons with PCI Express specification, this time is often referred to as the 100 ms boot time

requirement for PCI Express. In reality, the time that a PCIe core has to get ready for link

training is actually 120 ms

Welcome discussion.

[xytech]

see this. it maybe useful​

https://www.xilinx.com/support/documentation/user_guides/v6_pcie_ug517.pdf