Hi all.I'm working on a simple transceiver loopback test using a stratixIV GX development kit. I instantiated a simple ALTGX function in basic (PMA direct) mode, and i attached the altera loopback connector to the HSMC board. The reset sequence was done according to the reference documentation . The transceiver is fed by a simple counter, but on the receiver side i see the counter with the bits misaligned (eg tx: ABCDEF rx: EFABCD). Is this a known issue?What can I do to debug the design? I can provide as much info as you need, even the whole design. Thanks in advance Marco
this isnt a bug, you need to bitslip the data until it is aligned. generally there is a training sequence that is either spec'ed by the protocol, or is user specific.
Thanks a lot dwesterg,So for a "raw" transmission i need to implement myself a synch word and a FSM to realign the received data, right? But if i use a protocol (eg basic x4) i see in the signaltap anlyzer that the bits keep swapping. let's say the synch word is "0101111100", is it sent automatically or do i need to inject it periodically in the data? Thanks again! Marco (EDIT) the answer was yes, i need to inject the synch word and use an optional port to tell the transceiver when to realign. tnx