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Altmemphy DDR2 controller on CycIII, only mem_dq is changign

Honored Contributor II

Hi All, 


I am quite new to Altera and FPGA design, as a small project I am trying to code a DDR2 controller on Cyclone III development board. 



I have used Altmemphy DDR2 megafunction, and it responds my commands. For instance: 

  • it asserts "init_done" at the beginning 

  • sets "rdata_valid" sometime after I sent read request. 

However it does not create mem_... signals which are connected to the DDR2 modules on board. only mem_dq bus is changing in time, all others are 0



what I can observe are these: 

  • I attemt to write 3 blocks of data, and I can observe them in mem_dq signal, (A0A0A0.., BFBFBF.., CACACA..) 

  • However I can only read second one, when I read it (BFBFBF) 

Actually I am using phy_clk on SignalTap, and I know that it is not supposed to capture those mem_... signals, but it should be able to capture at least the changes of mem_addr? Am I right? 

Actually I also tried to use clk[0] which is generated for memory module for SignalTap clock, nothing changed. 



I attached my top design file, and screeshots from SignalTap during write and read phases. 



By the way I am using 50MHz cyristal as PLL ref, and 166.66MHz for Memory clock, and half rate 83Mhz for my design. 


Thank you in advance! :) 


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2 Replies
Honored Contributor II

did you simulate your design ? 


You can also try to reduce the speed to 133MHz or less. I had to reduce speed on an altera eval board to make my design work. The timing analysis was allowing 166MHz, the hardware was 200MHz compatible, but it didn't work at 150MHz but was ok at 133.
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Honored Contributor II

I guess i figured it out, thanks to support. 


They told me since those mem_... signals are time critical, using them with signaltap could cause some problems, so it is better to not observe them.. 


And thanks for reply, I will also try to lower speed, now i m working with 166MHz and half rate for my circuit. There is only a controller in my design.
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