11-25-2011 02:34 PM
Hi All,I am quite new to Altera and FPGA design, as a small project I am trying to code a DDR2 controller on Cyclone III development board. I have used Altmemphy DDR2 megafunction, and it responds my commands. For instance:
- it asserts "init_done" at the beginning
- sets "rdata_valid" sometime after I sent read request.
- I attemt to write 3 blocks of data, and I can observe them in mem_dq signal, (A0A0A0.., BFBFBF.., CACACA..)
- However I can only read second one, when I read it (BFBFBF)
11-28-2011 10:25 AM
did you simulate your design ?You can also try to reduce the speed to 133MHz or less. I had to reduce speed on an altera eval board to make my design work. The timing analysis was allowing 166MHz, the hardware was 200MHz compatible, but it didn't work at 150MHz but was ok at 133.
12-01-2011 02:00 PM
I guess i figured it out, thanks to support.They told me since those mem_... signals are time critical, using them with signaltap could cause some problems, so it is better to not observe them.. And thanks for reply, I will also try to lower speed, now i m working with 166MHz and half rate for my circuit. There is only a controller in my design.