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Connecting Wishbone I2C to NIOS2 in Qsys

Altera_Forum
Honored Contributor II
1,510 Views

I've seen a few posts related to this subject but they are all pretty old. I'm using Qsys, and I want to connect a Wishbone I2C core to the NIOS2 processor. I'm confused as to how to do this. 

 

I know the signals between Wishbone and Avalon are pretty similar - that's not the problem. 

 

The question is WHAT do I do in Qsys to hook the thing up??? Do I use some ready-made thing out of the library, like a Avalon MM pipeline bridge or something else, to hook it up? OR, do I do the 'New Component' thing? 

 

Surely somebody else has hooked the Wishbone I2C up to a NIOS2 processor before - is there some Qsys library component that somebody has that they can post? 

 

Thanks
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2 Replies
Altera_Forum
Honored Contributor II
141 Views

I did it several times, using the "New component" button, but I had to write a wrapper around the component to convert the Wishbone interface to Avalon. There isn't a lot to do IIRC, just something around the chip select and read/write signals. 

I don't think QSys supports the Wishbone interface natively (yet?)
Altera_Forum
Honored Contributor II
141 Views

I've performed this before in both SOPC and Qsys. Daixiwen is correct that it 

can be performed by creating a new component and attaching a wrapper hdl source 

file that links the Avalon signals to the Wishbone signals. SOPC/Qsys will 

analyze this file and generate the signals needed. 

 

An alternative method I use is to create a new component and link the core to 

the NiosII system in the top level hdl source. The new component definition does 

not include any source files. It has up to four interfaces defined for an 

Avalon MM-Slave, clock input, reset input, and interrupt sender. The Avalon 

MM-Slave interface should use addressAlignment NATIVE. Add signals for 

writedata, readdata, address, chipselect, write, and waitrequest_n to the Avalon 

MM-Slave interface. Add the clock, reset, and irq signals to their respective 

interfaces. Then add this new component to the system contents in SOPC/Qsys. 

The signals defined for this core will be added to the port I/O on the NisoII 

system module. 

 

 

The instantiation below is how I attached an I2C interface from OpenCores in 

the top level source. 

 

i2c_master_top# (.ARST_LVL(1'b0)) I2C_Master ( 

.wb_clk_i (clk_cpu), 

.wb_rst_i (1'b0), 

.arst_i (reset_n_to_the_I2C_Master), 

.wb_adr_i (address_to_the_I2C_Master), 

.wb_dat_i (writedata_to_the_I2C_Master), 

.wb_dat_o (readdata_from_the_I2C_Master), 

.wb_we_i (write_to_the_I2C_Master), 

.wb_stb_i (chipselect_to_the_I2C_Master), 

.wb_cyc_i (chipselect_to_the_I2C_Master), 

.wb_ack_o (waitrequest_n_from_the_I2C_Master), 

.wb_inta_o (irq_from_the_I2C_Master), 

 

.scl_pad_i (scl_pad_i), 

.scl_pad_o (scl_pad_o), 

.scl_padoen_o (scl_padoen_oe), 

.sda_pad_i (sda_pad_i), 

.sda_pad_o (sda_pad_o), 

.sda_padoen_o (sda_padoen_oe) 

);
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