Hi,1. I have some confusion about the bus number and device number we use in TPLs. For example if i connect a root complex with a native end point.... what will be the bus and device number for endpoint and for the root port?? I mean, how a device number and a bus number is assigned to an endpoint or device???? 2. One very confussing fact about the Altera's PCI-e core is.... when I send a type-0 configuration read TLP from the user side of root port, it reads the configuration space of root port rather than the end point. for example when i try to read the vendor ID of endport from root port using a type-0 configuration TLP.... the CplD indicates the vendor ID of root port... I am assuming that configuration space 0 always belong to the end point and configuration space 1 belongs to the root port.... Is is true???? 3. I am having some trouble while performing memory write transaction from end point to the root. The initialization steps that i followed includes........ i. I connected the phy sides of root port and the end point ii. Wait for L0 state. iii. Read vendor ID of end point from root side by using type-1 TLP :-)) iV. write BAR0 of end point from root side. v. read back BAR0 of end point from root side. vi. write BAR0 of root point from root side using type-0 TLP vii. read back BAR0 of root point from root side. viii.perform mem wr transaction from root side and checked the data at the user side of end point ix. perform mem wr transaction from end port and try to checked the data at the user side of root port However, didn't received any thing at the root port During all above steps whenever i use the root port to perform any transaction, i used the requester ID as (Bus# = 00, Device# = 00 and function# =0) and completer ID as (Bus# = 01, Device# = 01 and function# =0). I found that pattern from the simulation generated by IP compiler and dont know the reason.... In a nut shell, all the transactions performed from the root side were completed successfully but the transactions performed from end point don't behaves as it should!!!!!!!!!!! may be the device id/bus number is incorrect
I recommend you to try Jungo's windriver."It is free for first 30 days" You can at least perform config-read and endpoint read/write by using bar. so you can see if your h/w setting is correct or not. As far as I know, the PCIe core's config registers are working fine. I believe you can confirm your 1,2,3 by using the tool that comes with the Jungo's driver.
Hi,Have you resolve this problem ? I have the same problem when I try to use the altera pcie rootpoint to train the altera pcie endpoint. I can perform the mem wr transaction from root to end, but when I perform the mem wr from end to root, there is nothing in the avalon-st interface of the rootpoint. Is it the problem of the configuration ?