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Altera_Forum
Honored Contributor I
797 Views

Altmemphy Version 9.0SP2 --> 10.0SP1

Hi, 

i have a problem by generating a new altmemphy with Quartus 10.0SP1. 

 

The compile works with Q9.0SP2 but a new generation with Wizard 10.0SP1 make problems. 

 

This ist the error: 

Error: Couldn't find mimic clock from pattern |I_ddr3_controller|AlteraMemPhy|ddr3altmemphy|ddr3_altmemphy_alt_mem_phy_*inst|clk|*|altpll_component|auto_generated|pll1|clk[5] 

 

This ist the measureclk it can't find. 

 

Have any one an idea? 

Thanks!
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9 Replies
Altera_Forum
Honored Contributor I
31 Views

The best thing to do is probably to start a fresh project in Quartus 10 and rebuilt what you've made in Quartus 9. Otherwise you will probably encounter more errors like this. 

 

Also are you using the High performance controller and not the new High performance controller 2 in quartus 10? 

 

Overall you are quite vague :P.
Altera_Forum
Honored Contributor I
31 Views

Hi, 

 

For testing, i use the HPF2 Ctrl with dummy driver for testing the SODIMM. This works perfectly! The hardware have no problems. 

 

I'm not using the HPF 2 Ctrl for my project. 

I have to generate a new altmemphy for an older project, to implement it on our new hardware. We write our DDR3 controller by ourself, and it works on Stratix III. Im only want to regenarate the almemphy on Q10.0Sp1 on a Stratix IV. 

 

I use the same values as in the megawizard 10.0Sp1 as in 9.0Sp2. 

I don't copy the older core, i create it new. But the error ist still there! 

 

 

Regards, 

Josef
Altera_Forum
Honored Contributor I
31 Views

I created a brand new variation in 10 sp1 and still get this error. I followed the instructions provided by the megawizard to the letter... except to set the top-level entity in the project to ddr3_ip_example_top. Why would I want to do that if I am instantiating the design in my top-level? 

 

 

From the DDR Megawizard generator 

Info: Generating the Example Design. 

Info: Generating the Pin Planner file. 

Info: Generating the Synopsys Design Constraints file for the example top level. 

Info: Generating the Synopsys Design Constraints file. 

Info: Generating the Timing Report script. 

Info: Generating the ALTPLL Megafunction instance. 

Info: Generating the ALTMEMPHY Megafunction instance. 

Info: Generating the Functional Simulation Model for ALTMEMPHY 

Info: Before compiling your variation in Quartus II, you should follow these steps: 

Info: - Enable TimeQuest under Settings, Timing Analysis Settings. 

Info: - Add the ddr3_ip_phy_ddr_timing.sdc file to your Quartus II project. 

Info: - Add I/O Standard assignments by running the ddr3_ip_pin_assignments.tcl script. 

Info: - Set the Default I/O standard to match the memory interface I/O standard setting. 

Info: - Turn on Optimize multi-corner timing in the Quartus II Fitter Settings. 

Info: - Please make sure that address/command pins are placed on the same edge as the CK/CK# pins. 

Info: - Set the top level entity of the project to ddr3_ip_example_top. 

Info: See the User Guide for more details.
Altera_Forum
Honored Contributor I
31 Views

Hi, 

 

the ddr3_example_top is only a help to understand, how to connect the DDR3 into your design. There is an ddr3_example_top testbench to simulate the ddr3 core with modelsim. The ddr3_example_top have two entities, one driver (to test the DDR3 core) and the DDR3 core itself. You can simulate these example_top or can compile it into your hardware. It should work. Then when you understand it, you can implement it to your design. 

 

Please, can you post your Error message? 

 

Regards, 

Josef
Altera_Forum
Honored Contributor I
31 Views

Hi Joseph, 

 

Sorry I didn't mean to hijack your post. Some one had suggested earlier to start fresh and I was just pointing out that it doesn't work that way as well. 

 

I wonder if anyone had any success with integrating the controller and can share their success. 

 

Sanjay
Altera_Forum
Honored Contributor I
31 Views

Hi Sanjay, 

 

the DDR3 HPF2 controller created on Q10.0 works on my hardware (Stratix IV GX230C4) with 400MHz. I use an Micron DDR3 single rank module with 2GByte. And i test our Hardware with the driver example from the megawizard. 

 

Only the dualrank modules don't want to work, in this point wa have still problems. If we need more memory above 4GByte we need dual rank or more. 

 

Regards Josef
Altera_Forum
Honored Contributor I
31 Views

Thanks for the feedback. I just learnt that ddr3 controller with altmemphy has problems when derive_pll_clocks command is run in the some other sdc file in the design project. So if anyone else is having a problem where the filters in the ddr3 controller phy related sdc files are ignored because the nodes cannot be found, try to scan all other sdc files and remove the derive_pll_clocks command. It will cause problems in the other sdc files... I do not yet have an answer for how to address that.

Altera_Forum
Honored Contributor I
31 Views

Hi Sanjay, 

 

if you remove the "derive_pll_clocks", you have to set all pll_clocks by yourself. Otherwise timequest have unconstraint clocks and can't analyze these clocks. If there are problems with "derive_pll_clocks", maybe it's another problem? 

 

Regards,  

Josef
Altera_Forum
Honored Contributor I
31 Views

The problem is solved, :p 

 

there are new ports on the altmemphy since version 9.1. 

And there is an undocumented input port named mem_err_out_n. If you tie this port to logic '0', Quartus removes the measure_clk from the core. 

Tie this port to logic '1' and the measure_clk isn't removed. 

 

Regards, 

Josef