Hi,I have a Stratix3 DSP development Kit based on EP3SL150F1152C2N FPGA. I use the Triple Speed Ethernet MegaCore ( 10/100/1000Mb Ethernet MAC with 1000 base-X/SGMII PCS). When I load the design in the FPGA -> OK . But when I load the "simple socket server" software application or other software applications I have this error message : "Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Pausing target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused". It's strange because there were two weeks I load the"simple socket server" without any error. I didn't make any modifications between this two weeks. Is it possible that FPGA is damaged? Or else ? I know it could be the "reset" signal of Nios2 but it is not. When I use the Triple speed Ethernet IP but without the "10/100/1000Mb Ethernet MAC with 1000 base-X/SGMII PCS" (for example 10/100/1000 Ethernet MAC) I can download software applications on NIOS2. :confused::confused::confused: If you have any question , don't hesitate. Best Regards, Jeremy.
Hi Daixiwen,The timing requirements are OK and pll configuration also. (Note that I use the standard design shiped with the dsp development kit) I think it may be the "reset" about the PHY MARVELL. Is it possible ? Best regards, Jeremy.
No, if this was the case you would have some problems with the network interface, but the processor would still respond.If it is the standard design the only reason I could think of is a failure on the board or the USB blaster... Do you have anything plugged on an extension connector? Could you try and download the reference design from the Altera site and use it instead? Maybe something went wrong with your .sof file
OK. I have two HSMC connector but I have nothing connected on it.I have two data converter card that I unpluged since I have had this issue. In the end of afternoon (France :) ) I could download software, so I tested again "simple socket server" and "web server" template but they doesn't work (any response when I "ping" and the RX_LED blink but no TX_LED). It's weird because I used the design shiped by altera and I make any modification. Tomorrow I will search again. Thanks for your help, Best Regards, Jeremy.
Hi Daixiwen,Yes. This error message (...FAILED...) appeared in the begining of the transfert of the sofware. But now, the transfert is OK and I have not this error message. Yesterday I discovered that if I don't use TSE (of course in SOPC builder), I can run software on niosII (and I don't have the error message above). If I use TSE and I don't assign the pins for enet_rx_p (that's to say : pin AA33) and for enet_tx_p(n) (PIN_W28) I can run software on NIOSII. If I use TSE and I assign the pins for enet_rx_p and for enet_tx_p(n) I have the error message above. Do you have an idea ? (The TSE above was configured to 10/100/1000Mb Ethernet MAC with 1000 Base-X/SGMII PCS). Other question : Do you have an example of design which use the 10/100/1000Mb Ethernet MAC (how to configure it, how to use it and connect it with the PHY MARVELL 88E1111) ? I read TSE MegaCore User Guide but I am a little confused with the different configurations. However I think 10/100/1000Mb Ethernet MAC coud be a good solution. What do you think about that ? Best Regards,
Now I'm confused... Are you using the reference design or your own project? Do you have the same problem with the CPU not responding when using the reference design?It seems that the reference design is using a RGMII interface instead. It could be easier to debug. The Altera driver already has all the required function to initialize the MAC and they should work for all kind of interfaces to the PHY.
I use the reference design and I have the same with the CPU. Hower, if I don't assign the pins for enet_rx_p and for enet_tx_p I can run software on NIOSII. This design use the TSE configured to 10/100/1000Mb Ethernet MAC with 1000 Base-X/SGMII PCS.I will test the others configuration of TSE. Thank you for your help. Jeremy.
I don't think we are talking about the same reference design. The design "stratixIII_3sl150_dev_niosII_standard" distributed with the kit already has everything and uses a RGMII interface. You don't have to assign any pins or do anything with it, not even compile it. Just take the .sof, use the .ptf for your software and try it. That way we can know if the problems comes from the hardware or four design.
It is strange because is use this design without any modification. I download the .sof and .ptf and I have the same issue whereas in the past I have no problem with it.For information, when I open the sopc builder and I open the TSE megacore already use in the SOPC system, the TSE is configured with 10/100/1000Mb Ethernet MAC with 1000 Base-X/SGMII PCS. The standard design I used is dated from the 07/2009 ( is that help ? ).
If you still can't communicate with the Nios CPU with the .sof file compiled by Altera for the kit, then it means that you have a hardware problem on the kit itself. You should contact your distributor to see if they can do anything.