FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5742 Discussions

Are the IP cores form the University Program (USB, Ethernet) available in VHDL?

Altera_Forum
Honored Contributor I
760 Views

Hello all! 

 

My question is whether the implementation in VHDL of the IP cores (Ethernet, USB, LCD, etc.) used in the Qsys examples of the University Program are available. 

 

I would imagine that there is code for the AVALON interface and some core code to implement the actual interface. I am interested on the actual interface. 

 

Thank you!
0 Kudos
1 Reply
Altera_Forum
Honored Contributor I
43 Views

What do you mean? the source code for the actual cores will not be available, as many of them are suject to licencing (so they dont want people copying them).

Reply