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Are the IP cores form the University Program (USB, Ethernet) available in VHDL?

Altera_Forum
Honored Contributor II
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Hello all! 

 

My question is whether the implementation in VHDL of the IP cores (Ethernet, USB, LCD, etc.) used in the Qsys examples of the University Program are available. 

 

I would imagine that there is code for the AVALON interface and some core code to implement the actual interface. I am interested on the actual interface. 

 

Thank you!
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Altera_Forum
Honored Contributor II
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What do you mean? the source code for the actual cores will not be available, as many of them are suject to licencing (so they dont want people copying them).

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