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Arria 10 DDR3 with Bank 3G and 3H

Altera_Forum
Honored Contributor II
1,253 Views

Hi all, 

 

I have a question about the bank usage for DDR3 memory in the Arria 10. 

I'm using the following hardware: 

 

Arria 10: 10AX115R3F40E2SG 

DDR3 memory: Micron MT41J128M16HA-187E:D 

Quartus Prime 17.0.0 

 

The present design of my board (new board) tries to use bank 3G and 3H 

but when I tried to do "Fitter" with these banks by using the example code 

generated by the Quartus, the Fitter was failed. Then, when I did the same 

thing with bank 2L and 2K, it worked well. 

In the readme file (Section 6 Pin location), one bank for address and one of DQ/DQS/DM (x8), 

where most of pins are in this bank, and the other bank just for the remaining DQ/DQS/DM (x8). 

So I used 3H (48 pins) for the former and 3G for the latter because 3G has only 47 pins 

(there is no 0 index pin in this bank.) 

 

My question is cannot we use 3G and 3H for DDR3 in the above Arria 10 with DDR3? 

If there is a way to avoid this issue, I'd like to know it. 

 

regards, 

Junichi
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4 Replies
Altera_Forum
Honored Contributor II
142 Views

Tried to remove all location assignment for the DQ/DQS/DM (x8) in bank 3G. 

The only force one DQS pin with constraint as below see if you can fit the DQ/DQS/DM (x8) in bank 3G. 

set_location_assignment IOBANK_3G -to <dqs pin name> 

 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor II
142 Views

Thank for your answer. 

Concerning your suggestion, what does happen for the removed pins? 

 

BTW, after some iterations, I managed it. 

What I did is to use bank 3H for both DQ but 

when I used 1-11 and 12-23, the Fitter did not pass but 

when I used 12-23 and 36-47, the Fitter finished w/o error. 

 

regards, 

Junichi
Altera_Forum
Honored Contributor II
142 Views

For those remove pin, quartus will auto fit it to a location that meeting the fitting requirement. 

 

Yes, your observation is expected. You have to use I/O lane that adjacent with each other. 

See Figure 93. I/O Bank Sharing of EMIF handbook 

https://www.altera.com/documentation/hco1416493470528.html#hco1416492629263 

 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor II
142 Views

Thank for your answer. 

 

Concerning the automatic pin assignment, I tried it and found that this is very useful. 

 

Concerning Fig 93, I read it and what I said, that is, 

[1] 1-11 and 12-23 (bad case) 

[2] 12-23 and 36-47 (good case) 

both of them may satisfy this condition, I think. 

If you are talking the "adjacent" lane, [2] may not satisfy the condition but it's OK in the Fitter. 

 

BTW, concerning the address (a[13:0]), we have to use only the specific pins. I mean that can't we swap them among address pins? 

 

regards, 

Junichi
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