Arria 10 DDR4 IP - Using Hyperlynx DDRx Batch Wizard With Failed Simulation Results

[ConnorSousa]

Hello,

Device: 10AX066K2F40E1HG

We are designing a DDR4 LRDIMM interface for the above device using the EMIF IP.

We have a board layout, and we are attempting to complete simulation to verify the PCB. We have been using this guide for simulation:

https://community.intel.com/t5/FPGA-Wiki/Arria-10-EMIF-Simulation-Guidance/ta-p/735201

Under the "System-level timing closure" heading, we see the following statement:

"Note: Please do not use any simulation tool to perform system-level timing closure. Use simulation software to obtain channel loss and board skew data. Quartus will close the system level timing for you once you have entered accurate Memory Timing and Board timing information in the IP."

We are using Hyperlynx to extract the channel loss/crosstalk values used for the Quartus IP parameters. Our issue is that some of the nets (BA0, ODT0 specifically), are failing timing in the Hyperlynx DDRx batch wizard. Due to these failures which I have chosen to ignore following the above quote, the Channel Loss Calculation Tool from the Simulation Guidance is failing (I have already worked with Mentor Graphics on this, we are certain that the failing nets (ODT, BA0) are causing the excel channel loss tool to fail). If we delete the failing net rows from the DDRx Wizard results, then the channel loss tool completes.


My question is: Should I be ignoring the timing failures from Hyperlynx, relying on the Arria 10 IP to close the timing? If so, how do I properly pass the DDRx batch results through the calculation tool such that I get good results?

Note: The example data given with the calculation tool have no failing nets, indicating that all nets passed the Hyperlynx DDRx Wizard at the time they were produced.

Attached is the DDR report from the Hyperlynx Batch Wizard. Inside there is a .exe file which will open an explorer for the simulation results. The failed lines can be seen on the address tab.

[AdzimZM_Intel]

Hi ConnorSousa,

Thank you for submitting your question in Intel Community.

I'm Adzim, application engineer will assist you in this thread.

You can refer to Arria 10 simulation guidance flow to simulate the board simulation.

Link: https://community.intel.com/t5/FPGA-Wiki/Arria-10-EMIF-Simulation-Guidance/ta-p/735201

• I think you can take the value and use it to configure the EMIF IP.
• Timing closure can be done in the Quartus software.

Regards,

Adzim

[ConnorSousa]

Adzim,

I did follow the guide you posted. I am concerned that the Channel Loss Calculation Tool is unable to handle signals that did not pass timing during the Hyperlynx DDRx Batch process, but we are told that we should not expect our simulation software to close timing.

How am I able to tell how bad the failed Hyperlynx timing is? Surely the DDR4 IP cannot close any arbitrary timing violation, so what is the actual usable range?

I can simply remove the failed signals from the simulation data and run the Channel Loss tool, but am I potentially making some wrong assumptions in doing so.

[AdzimZM_Intel]

Hi ConnorSousa,

I'm sorry for the delay in providing reply to you.

I can suggest to you to refer to Arria 10 Design Guidelines document for more details on testing the board.

I'm not sure why you're getting the bad timing result which will be failed to test in the excel file.

I've asked for more details about the Channel Loss Tool from the engineering but they cannot done it yet because of limit bandwidth.

Please let me know if you found a better result when you doing the board simulation.

Thanks,

Adzim

Regards,

Adzim

[AdzimZM_Intel]

Hi ConnorSousa,

May I know if there is any question or update regarding to this thread?

Regards,

Adzim

[ConnorSousa]

I have already gone through the guidelines and I have already worked with Mentor Support regarding the Hyperlynx side. I believe my original question addresses the problem most accurately, so if any thorough investigation is to be done, I believe my original question is the best place to start.

On my end, we have already decided to move forward with fabricating our PCB. We used manual eye diagram simulation and static geometry analysis to ensure we complied with the guidelines of our particular device, so we were at least somewhat confident in ignoring the Hyperlynx+Channel loss tool combination as described in the guides. Fundamentally, it seems like having an LRDIMM with two ODT control inputs but only one ODT output on the FPGA (memory controller) is the major source of our headache. I don't believe the Hyperlynx DDRx batch wizard supports LRDIMMs directly, nor the special case I just mentioned.

Thanks,

[AdzimZM_Intel]

Hi ConnorSousa,

I'm not sure about the Hyperlynx DDRx batch wizard support memory type but maybe it's not able to test in this special case.

Since there is no further question, I will transition this thread to community support. If you have a new question, feel free to open a new thread to get support from Intel experts. Otherwise, the community users will continue to help you on this thread.

Thank you.