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Arria 10 EMIF for HPS IP "user logic" clock confusion

Mathis1
Beginner
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I am designing for an Arria 10 SX, using Quartus Prime Pro Edition

 

In order to connect the HPS to an external DDR memory, we can use the Arria 10 EMIF for HPS IP.

Within you can specify the memory clock frequency, while the clock rate of the "user logic" is supposed to be half of that.

There is however no "user logic" clock input to the IP, nor is there an AXI/Avalon MM interface connected to it that has an associated clock. The HPS is the one communicating with the IP so the "user logic" clock that is mentioned must be one within the HPS itself.

Reading the HPS technical reference manual shows that the L3 interconnect is connected to the SDRAM controller, so is "user logic" clock supposed to be the internal "L3 Clock Frequency"?

Or can I assume, since the HPS is the one doing all the communicating, that the clock relationship between the HPS and the HPS EMIF IP is handled automatically? It would be very nice if the only thing I had to consider is the memory frequency and the PLL reference clock of the IP.

 

I found a design made for a devkit that uses the HPS EMIF IP, and the value that the "user logic" clock was supposed to have(based on the memory frequency) did not exist anywhere in the design.

 

Thanks for the help

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khtan
Employee
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Hi

I'm sorry for the delay in getting back as it has been awhile on this case and I'm just checking whether you have resolve the issue at your end?

 

You're correct on this, the clock relationship between HPS and EMIF IP is handled automatically, just need to configure the memory settings in EMIF IP. Just some further information to connect the HPS to EMIF IP

 

khtan_0-1747732191487.png

 

khtan_1-1747732302055.png

Once again sorry for the delay in getting back

 

Thanks

Regards

Kian

 

 

 

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khtan
Employee
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Hi Mathis1,

Apologies for the delay in replying to this case as there is some backlog of issues on my end. I will look into the case and check whether is any documentation or example for this case.

 

Thanks and sorry for the delay

Regards

Kian

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khtan
Employee
380 Views

Hi

I'm sorry for the delay in getting back as it has been awhile on this case and I'm just checking whether you have resolve the issue at your end?

 

You're correct on this, the clock relationship between HPS and EMIF IP is handled automatically, just need to configure the memory settings in EMIF IP. Just some further information to connect the HPS to EMIF IP

 

khtan_0-1747732191487.png

 

khtan_1-1747732302055.png

Once again sorry for the delay in getting back

 

Thanks

Regards

Kian

 

 

 

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khtan
Employee
305 Views

Hi

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

 

Thanks

regards

Kian

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