Arria 10 EMIF writing to DDR4B data integrity issue

[rled64]

Hello dear community,

I'm using development plateform based on Arria 10 device (HAN Pilot) for data acquisition (ADC) project.
I have 16 samples of 16 bits incoming at a rate of 125 MHz (256bit wide writes), that I need to write to the FPGA side DDR4B memory through an EMIF IP. So I send write command to the EMIF at 125MHz as bursts depending on the sample window I want. The DDR4B_REFCLK is 266.66 MHz, and everything works fine I can write all my data without any loss.

Now I have new ADC project, which generates 4 samples of 8 bits on 8 lanes at a rate of 250MHz so I have consequently also 256bit of data to write through EMIF at 250MHz, but now the data I try to read back on the DDR4B is not consistent, there are some losses, etc...

My question is, is it related with the writing clock of 250 MHz which would be too close to the DDR4B_REFCLK frequency of 266 MHz ? 
Can I increase this speed ? I'm afraid I can't because I directly assign the refclk input clock from the board to the ddr4 clock in the top level design like this : 

.a10s_hanpilot_emif_ddr4bh_pll_ref_clk_clk                 (DDR4B_REFCLK_p),                 	  .a10s_hanpilot_emif_ddr4bh_oct_oct_rzqin                   (DDR4B_RZQ),                   .a10s_hanpilot_emif_ddr4bh_mem_mem_ck                      (DDR4B_CK),                      
.a10s_hanpilot_emif_ddr4bh_mem_mem_ck_n                    (DDR4B_CK_n),                    
.a10s_hanpilot_emif_ddr4bh_mem_mem_a                       (DDR4B_A),                   .a10s_hanpilot_emif_ddr4bh_mem_mem_act_n                   (DDR4B_ACT_n), 
....             

Should I write with a slower rate but bigger write size while I believe 256b is already the maximum writing size ?

Thanks for enlightning me !
 

[rled64 · Accepted solution]

Hello everyone,

I found the issue, it was not related with the writing speed of 250MHz since 266MHz ref clock is only for EMIF reference clk, and it writes at 1066MHz.
The issue apparently was some clock timing requirements which were not met. I had 2 external references clocks for my top level design (50MHz and 100MHz) which were not synchronous.