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mem
Beginner
64 Views

Arria 10 JESD204B Interoperability Reference Design timing issues

 

IP core Arria 10 JESD204B AD9144-AD9625 Interoperability Reference Design uses the following attribute for register duplication :

altera_attribute of normal : architecture is "-name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON;   ....  "

Quartus 19.1 ignores the register duplication attribute and we cannot get the required timing. All the failing paths have the following node as a starting point :

u_jesd204b_ed_qsys|jesd204b_subsystem_0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out

We tried several ways to convince Quartus to automatically duplicate registers in these paths, but it keeps ignoring all settings for register duplication.

Is there an attribute suitable for Arria 10 for register duplication?

 

 

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3 Replies
KennyT_Intel
Moderator
32 Views

Any reason that you want to duplicate those register? Are this for timing closure? If yes, can you send us a screenshot of the timing violation.


Usually you can see the duplication failure in the fitter/synthesis reports. Can you check on it? it will show the failing reason. But I think this feature only exist in the latest Q20.4, can you upgrade your Quartus to latest version?


KennyT_Intel
Moderator
15 Views

any update?


mem
Beginner
12 Views

At this point we have tested every design provided by Intel for jesd204b for Arria10

and we are a bit confused. We are interested to purchase a license for jesd204b from

Intel.

 

Any support is appreciated,

Thank you.