Community
cancel
Showing results for 
Search instead for 
Did you mean: 
SSD001
Beginner
43 Views

MAX 10 Ethernet Error

Hi Friends

I am using a MAX 10 CPLD (10M16SAUI169I7G) which is connected to LS1012A processor using 10/100  Media independent Interface.The max10 is used for acquiring the data from the ADC based on the instruction from the CPU.The MAX10 does not receive the UDP packets  from the processor at random time.The Triple speed Ethernet IP receiver is configured in promiscuous mode.
 
 
ETHERNET IP CORE USED : Triple Speed Ethernet 18.1
 
CPLD Used : 10M16SAU169I7G
 
Processor Used In Board : LS1012A
 
Mode of Communication between in Processor and CPLD : Media Independent Interface 10/100
 
Software Tool used : Quartus Lite Version 18.1
 
IP Core : Triple Speed Ethernet
 
CPU USED : NXP layerscape 1012A Low Power Communication Processor  
 
CPU Part number : LS1012A
 
At the Time of the Ethernet hang i am receiving data at the PHY chip level but when i set the Trigger at ff_rx_sop (rising_edge) the Signal Tap analyzer  the file says it in acquiring state as shown in the image  below.
 
With Regards
S.D.Shandeep
0 Kudos
1 Reply
Deshi_Intel
Moderator
19 Views

Hi,


From your signal_tap debug, that means it doesn't detect any assertion of ff_rx_sop signal. Nothing is coming out from TSE MAC Rx to FPGA core logic

  • It's either something is already corrupted from PHY Rx to FPGA Rx side
  • or some issue with your signal_tap sampling clock (fpga_mii_tx_clk)


You can set signal_tap trigger condition to "don't care" stage instead of trigger rising edge


Also you can probe TSE rx_err[5:0] to try identify what kind of error that you are facing


Another common debug approach is to enable TSE internal loopback to isolate whether the issue is inside FPGA or outside on your board setup


Thanks.


Regards,

dlim