FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6379 Discussions

Remote Update IP for Cyclone V -> Can any of the listed config devices support PS or FPP scheme?



‘Remote Update Intel IP’ for Cyclone V FPGA listed the following supported Configuration devices :

  • EPCS1/4/16/64/128
  • EPCQ16/32/6/128/256/512
  • EPCQL256/512/1024
  • EPCQ4A/16A/32A/64A/128A
  • MX25L128/256/512
  • MX25U128/256/512
  • MX66U1G/2G
  • S25FL128/256/512
  • MT25QL256/512
  • MT25QU256/512/01G

The first 4 look to be for Active Serial (AS) Configuration devices. Please confirm

Looking for any in the above list that can be used for Passive Serial (PS) or FPP (Fast Passive Parallel mode). 

Our current configuration device we use is FPP 1Gbit 16-bit (using CFI Parallel Flash S29GL01GT type (128Mx8, 1GB)).

Could revert to PS mode if we target a CFI parallel flash or a Quad SPI flash instead.

Can any of the above listed configuration devices support PS or FPP configuration scheme? Our first choice is to use FPP but if neither of the above configuration devices support FPP, can any support PS instead?

Seen the following link just now wrt Intel Tested and Supported Flash Devices :

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/support-centers/configuration-support.html   -> Intel supported Configuration devices

Under Cyclone V, it just lists :

  • MT25QL128/256/512/01G/02G (Micron)
  • MX25L/128/256/512 (Macronix)
  • S25FL/128/256/512 (Cypress)

This table just mentions Active Serial ASx1 & ASx4 schemes. 

  1. AS x 1 - Active serial configuration support 1 bit data width
  2. AS x 4 - Active serial configuration scheme support 4 bit data width

So above do not support PS or FPP configuration schemes?


Your prompt reply to this matter will be appreciated.




0 Kudos
4 Replies

Section 1.2.1 Table 1 of the following doc :


lists all supported CFI flash memory devices of the PFL intel FPGA IP core for configuring the FPGA in passive serial (PS) or fast passive parallel (FPP) scheme. Is this the case? Please confirm.

If yes, all below 4 look to be Passive Serial (PS) configuration devices and not parallel (ie Fast Passive Parallel (FPP)) ones after looking at their individual datasheets :

  • MT25QU02GCBB (2Gb) listed but we use a 1Gb density one
  • S25FL129P (128Mb) - S25FL129P device is backward compatible with the S25FL128P (uniform 256 KB sector) device
  • MX25L25635E – This matches the MX25L256 supported configuration list above
  • MX25U6435E listed for 64Mb but the supported configuration list above that we are trying to match lists 128Mb/256Mb/512Mb

It did not display the data width of the above configuration devices, just their density value but if they are all Passive Series (PS) types, data width will be just 1bit.

Please confirm if all 4 above are PS types

Can we then use the MT25QU01G (1Gb) that is listed within the compatible ‘Configuration Devices’ of the Remote Update Intel IP for Cyclone V FPGA as a PS configuration type (this has the same 1Gbit size to the one we are currently using (ie S29GL01GT, 1Gbit 128Mx8) and then use a S2P converter to the output of the 'Remote Update Intel IP' data/addr lines and connect its parallel output to the parallel PFL ?

This Configuration device matches also the density value of 1Gbit to the one we currently use. But the supported CFI flash memory device by the PFL Intel FPGA IP core for eg PS scheme is the 2Gbit version MT25QU02GCBB reported above. Will this be an issue if we try to use the MT25QU01G ?  Please comment here..

0 Kudos

I looked at the Remote Update IP today and when I select MT25QU01G as the configuration device, I also enabled all 3 following options :

   Add support for writting configuration parameters

   Add support for Avalon interface

   Enable recording POF checking

The avi_csr_writedata (in) and avi_csr_readdata (out) ports are 32bit wide & address shown in the block symbol asmi_addr (out) is 32bits wide too.

With MT25QU01G as the configuration device, if we write to avi_csr_writedata a 32 bit value can we then read the 32 bit value out of avi_csr_readdata as parallel data in just one clock cycle if eg the address used to write and read is at offset 0x3 (Register RU_PAGE_SELECT) to avl_csr_address(2:0) with a value of 0 ?

Register RU_PAGE_SELECT in reality will represent reading or writing the start address of configuration
image.  So if we read out the 32bits value in 1 clock cycle we will NOT require to use a S2P converter at the output of the 'Remote Update Intel IP' data/addr lines and connect it directly to the parallel PFL.

We are planning to just use 16 low bits (15:0) of data and 26 low bits (25:0) of address to connect to out parallel flash x16 corresponding data/addr lines. 

Please can someone reply to let me know if my assumption here is correct ie S2P conversion will not be required if we get parallel data coming out of the Remote Update IP with the MT25QU01G selected as the configuration device?

0 Kudos



If you are referring to PFL IP user guide, MT25Q is supported. The list of supported flash is available at link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf (Page 4)


Yes, PS / PFL configuration scheme is supported by cyclone v.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdf (Page 243)


For MT25QU01G, it is not listed in the documentation. But if the instruction set of the device and pin connection are the same as 2G, I don’t see any problem in using it.


Yes, S2P conversion will not be required. If AVMM setting is enabled.


Thank You.




0 Kudos

We realised that this is thread is a duplicated thread of 04988636. I am now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

0 Kudos