Arria 10 Transceiver PHY Initial calibration

[CHebl]

Hi All,

I designed a board with an Arria 10 FPGA, which doesn't supply the Transceiver reference clock pins with an initial free running clock (CLKUSR is present though).

For this reason the inital calibration process of the PreCISE engine fails and all *cal_busy signals stay asserted.

Is it okay to start a reset sequence (assert analog and digital resets) even though the cal_busy flags are asserted and subsequently after doing reconfiguration start PreCISE calibration?

Many thanks for help.

Cheers