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Altera_Forum
Honored Contributor I
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Arria 10 Transceiver PHY latency estimation

Hi,  

 

I want to calculate/estimate the latency incurred in transmitting data from the Arria 10 Transceiver PHY IP. I looked into the user guide; it doesn' have any discussion on latency of the blocks, or latency occurred from data received from the FPGA fabric to serial data transmitted from the PMA buffer. My application requires a deterministic latency for the Transceiver PHY and the only thing I could find in the user guide is "the Register Mode [in Standard PCS options] bypasses the FIFO functionality to eliminate the FIFO latency uncertainty for applications with stringent latency requirements."  

 

Please let me know how could I estimate the latency of the Transceiver PHY in transmitting data.  

 

Thanks, 

Arvind
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