FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5881 Discussions

Arria 10 Transceiver PHY latency estimation

Altera_Forum
Honored Contributor II
812 Views

Hi,  

 

I want to calculate/estimate the latency incurred in transmitting data from the Arria 10 Transceiver PHY IP. I looked into the user guide; it doesn' have any discussion on latency of the blocks, or latency occurred from data received from the FPGA fabric to serial data transmitted from the PMA buffer. My application requires a deterministic latency for the Transceiver PHY and the only thing I could find in the user guide is "the Register Mode [in Standard PCS options] bypasses the FIFO functionality to eliminate the FIFO latency uncertainty for applications with stringent latency requirements."  

 

Please let me know how could I estimate the latency of the Transceiver PHY in transmitting data.  

 

Thanks, 

Arvind
0 Kudos
0 Replies
Reply