Parallel Flash Loader For MAX II .

Altera_Forum · ‎07-13-2018

Hi Everyone,

I am using the Parallel flash loader for CPLD to configure an FPGA using an on board NOR flash.

I have been able to generate the IP by following AN478 and AN386.

I have instantiated a flash_inst from my CPLD top file. The Flash QIP is called from the flash_inst.

My question is , do I have to generate the test bench for the flash_inst, which is calling the Flash IP?

Thank you in advance.

Altera_Forum · ‎07-18-2018

Hi,

--- Quote Start ---

My question is , do I have to generate the test bench for the flash_inst, which is calling the Flash IP?

--- Quote End ---

Not required.

Refer the “Using the PFL in the Quartus II Software” from the AN386.

1. Intel/Altera recommends setting all unused pins to tri-state.

2. Instantiate the PFL Megafunction in the Quartus II Software by referring “Instantiating the PFL Megafunction in the Quartus II Software”.

3. Then obtain .pof file for Flash device.

4. Program the Flash device by referring “Programming MAX II and Flash Devices”

Which Quartus Edition & Version are you using?

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)

Altera_Forum · ‎07-18-2018

Thank you for your reply Vikas.

I am using the Quartus II 17.1 Standard edition.

I have followed the steps told by you and in the AN386.

My question was, do I need to generate a test bench for the vhdl file which calls the IP.

Regards,

Altera_Forum · ‎07-19-2018

Hi,

--- Quote Start ---

Hi,

My question is , do I have to generate the test bench for the flash_inst, which is calling the Flash IP?

Not required.

--- Quote End ---

what are you trying to do with test bench?

if you wish to configure FPGA then refer previous post.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)