The board I am designing has 9 8Gb DDR4 memory chips, for a total of 72 DQ lines (8 per chip). I want to verify that all chips are present and working by reading and writing to an address on each chip, using the NIOS II Core via EMIF.
The way I see it at present, using the Address Span Extender, I can only access concurrent blocks of memory, which would mean using up a massive amount of NIOS memory addresses which I don't need to use.
Is there any way to map the NIOS to the DDR4 such that I can smaller spaced out address windows? I thought the offset would be an offset between windows, but infact just offsets the base address. If more than 2 windows are set, this option is even disabled from changing.
Is there a suitable way to implement such a test with the NIOS and DDR4? Perhaps there is some way I can use DMA to test all the RAM, store results in a register and check that with the NIOS? I'm not sure how I'd implement something like this - I am new to FPGA.
Any and all suggestions are appreciated, thanks.
Please accept my apology for the delay in response due to workload.
If you want to access a larger address map than the width of their address signals allowed, then the best option is using this Address Span Extender.
Yes, you can also use DMA to access the memory. You may want to refer to this handbook which have more information regarding DMA engine. --> https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/edh_ed_handbook.pdf