FPGA Intellectual Property
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Arria 10

qiaomeng
Beginner
129 Views

Why is the locked output of my iopll phase-locked loop not pulled high, but I want to get a 10M pll output clock, the actual test only generates 5M, what could be the problem, my FPGA is Arria10?please ,my email is qiaom@mail2.sysu.edu.cn

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1 Reply
Ash_R_Intel
Employee
106 Views

Hi,

Check the signal integrity of the input clock. Is it differential? If yes, do you have proper termination? Are the voltage supplies stable?

Check the Pin Connection Guidelines of the device.

Regards


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