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Asynchronous/ controlling clock port of a flipflop

Altera_Forum
Honored Contributor II
960 Views

Hello All, 

I am wondering if i can explicitly define a clock port to a flip-flop(D-FF or T-FF). The functionality should be like this, I need to sample a date input with respect to a positive-rising edge of a control signal. I am aware that you can use enable port in the flip-flop but i need to sample the data line exactly at positive rising edge. 

 

Regards, 

Dilip
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
90 Views

A flip-flop samples the data input always exactly at the positive (or negative) rising edge of it's clock input. It's no problem to use a control signal other than the system clock as clock for a FF, but then it's output is asynchronous in respect to the system clock and has to be synchronized.

Altera_Forum
Honored Contributor II
90 Views

I get that. I want to know how to use a control signal other than the system clock as clock for a FF. As i can see the clock port is implicit.

Altera_Forum
Honored Contributor II
90 Views

Oh I am sorry. All these things am talking about is concerned to Alters DSP builder on Simulink.

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