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Avalon I2C (Master) Core only supports MM interface -OR- ST interface, not both

Altera_Forum
Honored Contributor II
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The Avalon I2C (Master) Core only supports memory mapped access to the command and receive FIFOs -or- streaming access to the FIFOs, not both. This isn't precisely a bug, but is poor design. There's no reason that selecting the streaming access to the FIFO option for the I2C Master in QSys shouldn't allow either. 

 

I'm tempted to "fix" it in the altera_avalon_i2c_csr.v file, but I'm not sure of the ramifications. Has anyone tried this? 

 

Of course, the downside is that the library would have to be pulled out of the QSys flow so that it didn't keep getting overwritten by the standard library (at least, that's my understanding of how QSys works). 

 

Further, it appears that the Nios II I2C driver only supports the memory mapped version. This seems reasonable enough, given that the Nios II doesn't _have_ a streaming port, but does make things inconvenient. 

 

Maybe the simpler thing is to acknowledge defeat and write my own I2C driver for the Nios (utilizing a custom memory mapped streaming channel chunk of verilog). 

 

Thoughts? 

 

Calvin
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