Avalon Interconnect Dynamic Bus Sizing and Bursts

[sadad]

Hello!

My Avalon-MM master has 32bit data width and is bursting capable.

Now i connect an Avalon-MM slave with 8bit data width which is also bursting capable.

Will a 32bit read or write access to the slave cause the automatically generated Avalon adapter to translate the 1x32bit access to a single burst of 4 x 8bit?

Or will there be 4 non bursting transfers of 8bit?

Thanks in Advance!

[sadad]

Would you please mark the important regions in your screenshot? I can not see any signal regarding the burstcount. I can only see that burstcount is in an invalid state 'X'.

I checked your qsys design => the onchip ram has 32bit avalon mm bus => so there wont be any translation.

[sadad]

Is the onchip_ram even bursting capable? I don't think so. i cant see any bustcount signals.

[Kenny_Tan]

Yes, it is supported. you can't see the burst count because the screenshot does not show the whole waveforms. You can try run the design attached to see it.

Thanks

[sadad]

in your design i could not see any burst signals to the onchip ram in the qsys schematic view , so i think there will be a bursting adapter in your interconnect.

=> would you show me a screenshot of your qsys schematic

[Kenny_Tan]

Yes, it should be on the bursting adapter. You can check where does the adapter being inserted in the qsys.

in qsys -> press system -> show system with interconnect -> memory mapped interconnect

You can also explore what it have under system with interconnect.

[Kenny_Tan]

any update?