Is it possible that the Signal tap logic analyzer changes behavior of the SPI core in Qsys? I'm working on Stratix 10.

[VBart]

Hi, recently it has been a concern that tapping on different signals with the Signal tap logic analyzer changes the behavior of the SPI core in Qsys. Tapping into different signals sometimes enable the writing of the SPI and sometime disables the writing. I can never predict the outcome of the logic analyzer. Is this a normal behavior on the Stratix 10?

Thanks

[RichardTanSY_Intel]

Signal tap logic analyzer unlikely to changes the behavior of the SPI core in Qsys. Could you kindly help to check if there any abnormality from the simulation?