Avalon MM FIFO

[greenlantern01]

Hello,

I am currently working with a DE10 Standard FPGA Board and a DC2390 Daughter Card. I am capturing the ADC values generated by the daughter card and then using a fifo in the qsys to store these values. The values are being captured on the FPGA and I intend to forward these values to FIFO, which will then be accessed by the HPS. 

I am trying to understand how to use the control status registers to manipulate the data write in the FIFO. Could you share some document which provides which bits in the registers denote what function?

Also, is there a timing diagram for the FIFO that I can follow?

Thanks in advance for your time and assistance!

[sstrell]

Embedded Peripherals IP User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683130/24-1/software-control.html

[greenlantern01]

Hello,

Thank you for your response! 

I am using an Avalon FIFO Memory in the Qsys and I have turned on Status interface port for input and output and turned off allow backpressure. It is in Dual Clock mode and input and output types are avalonmm write and read respectively.

The data is being captured on the FPGA from the DC2390 daughter card connected via HSMC. I want to forward this data from FPGA to FIFO and therefore have exported in the input, input reset, and the in_csr ports. 

Could you share what the above registers do? I couldn't find much about them.

Also, the in_csr_readdata register currently has bits 1 and 3 high (1). What should I interpret from that? 

[sstrell]

Without knowing what status register you are reading from, there's no way to interpret what you are asking.  They're all documented at the page I linked you to.  If you are talking about the i_status field, as that page says, these bits interpret to almostempty and empty as the chart there explains.

[greenlantern01]

The documentation is confusing to understand. 

These are the registers I see when I export the in_csr port from the FIFO:

1) wrclk_control_slave_address[2:0]

2) wrclk_control_slave_read

3) wrclk_control_slave_writedata[31:0]

4) wrclk_control_slave_write

5) wrclk_control_slave_readdata[31:0]

In the documentation, it only mentions status register. Is wrclk_control_slave_readdata the status register? Does it mean that  when:
bit 0 (when high) - FULL
bit 1 (when high) - EMPTY
bit 2 (when high) - ALMOST FULL
bit 3 (when high) - ALMOST EMPTY
Bit 4 (when high) - OVERFLOW
bit 5 (when high) - UNDERFLOW

If so, what do the rest of the registers do?

Thank you

[sstrell]

You are using the word "registers" incorrectly.  Those are signals, not registers, that make up the in_csr Avalon interface for checking the input side of the FIFO (writing data into the FIFO).  They control reading and writing the CSR (control and status registers) of the write side of the FIFO.

In the document, table 269 is showing you the entire register map of this interface.  So if you do a word (32-bit) read on this interface at the base address you've set for the in_csr interface in Platform Designer, you'll read the 32-bit fill_level register which is described in table 270.

If you do a read on this interface at the base address + 1 (which may be plus 4 if your host interface is using byte addressing which is the default in Platform Designer), you advance to the next 32-bit word which only includes the 6-bit i_status register where each bit is documented in table 271.  The upper 26 bits are unused.

This is how basic memory-mapped addressing works and how it is documented everywhere, so if you are not familiar with this, you may want to do a little googling.

You can also look at the Avalon interface spec here: https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/introduction-to-memory-mapped-interfaces.html.

[greenlantern01]

Understood. So then, the only way to access these registers would be to then create a C file that does the memory mapping and then does a read operation to read from the FIFO? 

Can I monitor the registers in SignalTap? 

Can you also share the link in the documentation where it mentions how to use the control and status signals?  The ones that I mentioned in my previous question.

P.S. Thank you for the quick response and detailed explanation.

[sstrell]

Well when you're talking about C, you're going to a higher level language and assuming that you have a processor that can interpret that code and access the registers.  The document goes into that with the API: https://www.intel.com/content/www/us/en/docs/programmable/683130/24-1/intel-fpga-avalon-fifo-memory-api.html

You can monitor the interface *signals* in Signal Tap like you've already done.  You may be able to tap the registers themselves but that can be hit or miss with an IP.  You looked at the wrclk_control_slave_readdata signal which, depending on the address put on the interface (wrclk_control_slave_address), would show the data stored in one of the registers in the register map, like i_status as I mentioned.  So the idea is to, in Signal Tap, correlate between the address put on the address signal and the data retrieved on the readdata signal.

The Avalon specification I already shared details the signals that make up the Avalon interface and it includes timing diagrams to understand their use.

[greenlantern01]

Gotcha! Thanks.

Where can I find more info on the wrclk_control_slave_readdata signal and other such signals?

The link you shared mentions about the in_read/in_write and in_readdata/in_writedata.

I would like to know about the csr_readdata and csr_read signals. I read somewhere that different bit of the in_csr_readdata  represents levels such as full, empty, almost full etc. So I just wanted to know if I can use it to control the write operation from the FPGA end in the FIFO.

Thank you!

[sstrell]

They're all in the same document.  Click around or download the pdf: https://www.intel.com/content/www/us/en/docs/programmable/683130/24-1/interface-signals-02827.html

And I already said that when you read the readdata signal, depending on the address you access, the particular bit corresponds to the full, empty, etc. flags you mention as described in table 271.  There aren't dedicated signals for these flags if that is what you are asking.

And again, the general function of each signal (readdata, writedata, read, write, address, etc.) is governed by the Avalon standard described in the Avalon spec I linked to.