FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5990 Discussions

Avalon MM Master simulation problem

Altera_Forum
Honored Contributor II
798 Views

Hi 

 

I have designed an Avalon MM write master that writes data to onchip memory.  

 

I built a NIOS II system in qsys (V13.0sp1) and ran the system however the waitrequest on the Avalon Master always remains high in the modelsim simulation.  

 

It has been working.  

 

I changed the following line 

 

assign avm_write_master_write = (write_state == MID_BURST || write_state == FINAL_BURST)? 1 : 0; 

 

to 

 

assign avm_write_master_write = ((write_state == MID_BURST || write_state == FINAL_BURST) && avm_write_master_waitrequest == 0) ? 1 : 0; 

 

As the former was clearly buggy.... although the latter causes the write signal to stay low as the wait request is always high..... (in the former the wait request went low).....  

 

Anyone got any ideas?  

 

Rob
0 Kudos
0 Replies
Reply