DDR3 Performance changes with different pinout

[Altera_Forum]

I have proven FPGA code in a Stratix IV GX that uses the NIOSII, Altera Video Suite IP components, and DDR3 Uniphys for the NIOS and Video buffering. On a previous board design, we were able to achieve at least 40MHz throughput. 

In a new board design that required a different pinout, the performance has dropped to about 350MHz.  I am trying to understand why the performance would change so significantly.

[Altera_Forum]

Hi, 

 Are you using different FPGA device? Previously which FPGA device are you using for DDR3 UniPHY interface?

[Altera_Forum]

Although the board design is different, the FPGA device is the same. The pin-out of the FPGA is different.

[Altera_Forum]

- Are the settings the same inside the megawizard GUI? 

- Are you using the same Quartus II version to generate the design?

[Altera_Forum]

The megawizard didn't change and we are using the same version of quartus.

[Altera_Forum]

You're meeting all timing?