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Honored Contributor I
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Simulating ALTFP_FP_ACC_CUSTOM core

Hello everyone, 

 

I have multiple floating point cores from Altera as part of my design. Such as FP multiplication, addition, log, sqrt and a few others. I use Quartus II v 13.1  

 

I've been simulating my design using ModelSim-Altera. So far the procedure I've followed is to add the VHDL files generated by the Megawizard to the ModelSim library, compile and then run simulation. This has worked for me so far. However I just added the Custom floating point accumulator and it seems to have a different operating procedure for simulation which I am unable to figure out. The wizard created a VHDL file in my Quartus project directory in addition to three other files. I assummed I must add the VHDL files generated in the "-SIM" folder which it created. However this doesn't seem to work.  

 

I am unable to compile these files in ModelSim. The component declaration in the generated file declares output ports of type std_logic whereas another file with the original entity has declared the same ports as std_logic_vector( 0 downto 0). Thus leading to type mismatch errors in ModelSim. Now, these are files generated by the MegaWizard and I have not altered them in any way . I am guessing there is some other procedure I must follow to simulate these files. Would appreciate it if someone could direct me to it.
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