I am using Stratix 10 SoC dev kit & working with FPGA-DDR4 (16GB) interface. When I enable the 72 bit data width (64 bit data + 8 bit ECC), the user data width(AV-MM) is 576 bit. My assumption is first 512 bit is corresponding to user data width (64) * 8 (burst of
I am not using ECC feature of DDR4. So can I do data write & read to DDR4 by ignoring MSB 64 bits (575-512) of data?
I got the reply through mail as below.
Yes, you can data write & read to DDR4 by ignoring MSB 64 bits (575-512) of data.
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