Avalon-MM datawidth handling for DDR4 controller with ECC
I am using Stratix 10 SoC dev kit & working with FPGA-DDR4 (16GB) interface. When I enable the 72 bit data width (64 bit data + 8 bit ECC), the user data width(AV-MM) is 576 bit. My assumption is first 512 bit is corresponding to user data width (64) * 8 (burst of & next 64 bit (575-512) for ECC data.
I am not using ECC feature of DDR4. So can I do data write & read to DDR4 by ignoring MSB 64 bits (575-512) of data?