Avalon On chip Fifo

Altera_Forum · ‎02-08-2016

Hi all,

i'm having trouble with avalon Fifo core (dual clock mode).

I have a simple FSM that grabs data from a fifo(1) and then transmit the response to another fifo(2) but nothing is written as read level is 0.

But, if i write 3 times the same data in fifo(1) i get one response in fifo(2).

well i think i missed something there...

notes : interrupts are disabled, Almost empty = 1

init_fifos_in();    init_fifos_out();
 
    init_fifos_in();
    init_fifos_out();
    altera_avalon_fifo_write_fifo(FIFO_PC_TO_DIF_IN_BASE, FIFO_PC_TO_DIF_IN_CSR_BASE, 0x00004005);
    altera_avalon_fifo_write_fifo(FIFO_PC_TO_DIF_IN_BASE, FIFO_PC_TO_DIF_IN_CSR_BASE, 0x00004005);
    altera_avalon_fifo_write_fifo(FIFO_PC_TO_DIF_IN_BASE, FIFO_PC_TO_DIF_IN_CSR_BASE, 0x00004005);
    printf("pio read = x%x\n", IORD_ALTERA_AVALON_PIO_DATA(PIO_0_BASE));
    if(altera_avalon_fifo_read_level(FIFO_DIF_TO_PC_OUT_CSR_BASE)>0)
    {
           printf("altera_avalon_fifo_read_level(FIFO_DIF_TO_PC_OUT_CSR_BASE) = %d\n",altera_avalon_fifo_read_level(FIFO_DIF_TO_PC_OUT_CSR_BASE));
        while(altera_avalon_fifo_read_level(FIFO_DIF_TO_PC_OUT_CSR_BASE)!=0)
        {
            printf("fifo read = x%x\n", IORD_ALTERA_AVALON_FIFO_DATA(FIFO_DIF_TO_PC_OUT_BASE));
        }
    }
    }


status initializing fifo = 0
pio read = x4005
altera_avalon_fifo_read_level(FIFO_DIF_TO_PC_OUT_CSR_BASE) = 1
fifo read = x30c30c30

Altera_Forum · ‎02-09-2016

problem solved, fsm did not work properly (signal tap), although it was ok in simulation...