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Altera_Forum
Honored Contributor I
912 Views

VIP video monitor: expected number of pixels mismatch for Bitec HDMI input

Good evening. I'm sending video data from a Bitec HDMI RX core via a clocked video input to an Avalon-ST video monitor, in order to check if my HDMI input is OK. 

 

HDMI input core seems to work ok (clocks are locked, RX ready flag is on) and CVI sends video control packages with the correct resolution to the Avalon-ST monitor. 

 

My problem is that the video monitor reports (via Quartus system console and trace tool) a mismatch between the number of pixels delivered to it (packet length = ~4,000 pixels) and the expected number (~2,000,000). Pixel data is not shown correctly (with only 4,000 pixels delivered there's not much to show..). 

 

I have tested my CVI and monitor to work OK by creating a test image using the VIP test image generator and clocked video output IP. 

 

Has anyone else had this problem? Do I need to place a frame buffer in front of the video monitor or is the FIFO in the CVI core enough? 

 

Thank you, 

Klaus
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3 Replies
Altera_Forum
Honored Contributor I
41 Views

Quick update: I checked my CVI overflow line and saw that regular overflows are detected. Should those be prevented before or after the CVI (by e.g. using a frame buffer)?

Altera_Forum
Honored Contributor I
41 Views

If input and output of your system have different bitrate you should use frame buffer with frame rate conversion(it is one of frame rate conversion method). You can insert it in any place of your video path. Monitor does not affect the bandwidth

Altera_Forum
Honored Contributor I
41 Views

Thank you, that was the solution. After inserting the frame buffer after CVI II, things started working without problem. It is interesting that I wasn't able to get the system working with a FIFO only, whatever I tried. Even with only slightly different pixel clocks for input and output, CVI shut down with overflow immediately.

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