I currently am running a Nios II system based on SOPC Builder with separate RAM & ROM banks comprised of onchip memory. I have a requirement to update the the software while the system is running. In order to use the procedures used by other processors in the system, I need to implement a dual ROM bank version of my Nios system. One ROM bank will contain the currently running software. The second bank will be writeable abd will be loaded with a new copy of the software by a background software process. When the second bank has finished loading, the Nios will jump to the reset location and start using the second bank. All software is built to run in bank one. So, while jumping to reset, the bank addresses need to be swapped.My simplistic approach is to use SOPC Builder to create a custom Avalon-MM bridge between the Avalon fabric and the onchip memories. Then I can switch the upper address bit to swap the two bank. However, I cannot get a simple MM Slave to MM Master bridge to work. When I look at the waveforms in simulation, the 32 bit wide memory is being byte addressed four times with incrementing byte addresses for each instruction fetch. There may be other problems but I won't know that until I get this problem fixed. Is there a simple Slave-Master bridge example that works correctly that I can use as a starting point?
Are you only have 1 Nios II CPU in your system?My understand on your requirements is: (1) Nios II is requested to load a new software. (2) In the background, Nios II enter software loading routine, read the binary data from a source and write it to the ROM. In the foreground, Nios II still running normally? (So, you are running on an OS?) (3) Once writing finish, trigger a reset to the system (or just the Nios II), new software will be loaded from ROM to RAM, and Nios II start running with new software from RAM. Question: (1) How do you update the data in your onchip memory ROM? (2) Do you still need you foreground software to be functioning while background is loading new software into the rom. Answer to your question: (1) 32 bit wide memory is being byte addressed four times with incrementing byte addresses. Ans: This is always be the case, since Nios II have Instruction cache, and the cache line size is always 32bytes = 4 word. Whenever there is a miss on the instruction cache, Nios II is going to load the full 4 words to fill up the line. Why this is an issue for your system?
I am have very simple microcontroller based on the Nios II/e. There is no cache, no MMU and no OS. The new code image is downloaded by the Nios using an API to a board level processor who's Flash contains code images for all programmable conponents on the board.I spent about an hour and a half in a WebEx session with an Altera FAE and he found the problem. I constructed my bridge with the SOPC Builder Component Editor. I used the typical slave template and the typical master template and connected them back-to-back. As it turns out, the slave template uses a word address bus and the master template uses a byte address bus. Once the differences were accounted for, everything works as expected.