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Hi all!
For writing/reading coefficients I made a wrapper to compute the proper reset before accessing the Avalon slave.
Writing seems to work fine but reading has issues
Considering the FIR II IP Core User Guide and the read waveform:
As you can see they forgot to add the read signal (read enable) to the waveform.
If I capture the signals with the Signal Tap Logic Analyzer (Quartus 17.1), the behavior is completely different!:
As you can see in the waveform above the reset is right and the address and read signal is set after the same amount of clock cycles. 3 clock cycles later the proper data shows up on the read interface but the valid signal comes much earlier and therefore the behavior is wrong and does not correspond to the user guide.
Behavior in Quartus 15.1 is wrong as well as the valid signal is never set there!
I will provide later a capture with the Signal Tap Logic Analyzer.
Kind regards,
Erich
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Additionally both Quartus 15.1 and 17.1 the Fir filter still has the issue with the low active reset declaration in the _hw.tcl file but in fact it is active high! You can find a description here.
And here is the capture with Quartus 15.1:
First read the data output is 0x16 but valid never is set to high and at the end the end (yellow circle), the output changes but the valid not set to high.
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Hi Chee Pin!
It is not only a mismatch between manual and the implementation. The implementation is for sure wrong! In Quartus 15.1 there is never a valid signal -> so a Avalon Master will never return proper data.
In Quartus 17.1 the valid signal is much to early -> Avalon Master will receive wrong and too much data!
Regarding simulation, I tried to setup a simulation. If I enable the Coefficients interface in Quartus 15.1 it doesn't even compile. With Quartus 17.1 it compiled but it did not work at all -> therefore another bug(s) in simulation as well.
Best regards,
Erich
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Hi Chee Pin!
As I written in my previous post, the simulation does not work and does not behave as the real implementation -> therefore I started to capture data with the Signal Tap Logic Analyzer!
So setting up a simulation does not help. As I already wrote in an other post of a different topic.
Intel decided to stop the support requests and there is no NDA so I can not give company implementations to the puplic! So I cannot give you my project.
You could setup a project and capture real data with Signal Tap Logic Analyzer to see the issue. Same is true for simulation.
I will not setup Quartus 18.1 because as far as I saw there were no important changes. And if I have a look to the FIR filter release notes there were no changes after 17.1:
https://www.intel.com/content/www/us/en/programmable/documentation/hco1421697814795.html
Best regards,
Erich
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Hi Chee Pin!
Sorry for my late answer!
I will not install Quartus 18.1 as there was no improvement on FIR or Quartus itself. The only updates I saw were done for the Pro version.
I'm afraid I can not promise that I will get some time for setting up another simulation. And yes simulation does not work but this thread was created because the real implementation does not behave like the manual! You can see the wave forms in my first post. So maybe that should be forwarded to the developers so that they can have a look to that.
The developers should have a simulation for the FIR including the coefficient reload. They should know that it does not work! That is very basic.
By the way from the design perspective it is a very bad implementation because it is declared as Avalon Bus but it needs upfront a reset which is not the way how the Avalon Bus is specified!
Best regards,
Erich
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Hi Chee Pin!
Thank you for your image!
Above is your screenshot you send me per mail!
But you did not reset the coefficient interface like it is descriped in the FIR manual:
Looking forward to your answer!
Best regards,
Erich
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Hi Chee Pin!
If you have a look to mir first post and if you compare the waveforms from the signal tap then you will recognize that they look exact like the waveforms from the manual except that the valid is wrong.
Best regards,
Erich
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And here is the read from a Quartus 15.1 FIR:
Valid is always 0!
Best Regards,
Erich
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Hi Chee Pin!
Here your screenshots:
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Hi Chee Pin!
Do you agree that the behavior is different than described in the manual?
Best regards,
Erich
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Hi Chee Pin!
Really? Do I really need to explain it?
- First what you described here: https://forums.intel.com/s/question/0D70P000006INUJSA4
- Valid is always high!!!!!!!
- Read request is not necessary! Why is there then a read request signal?????????????????????????
- Data changes one clock cycle after, the manual states 3!!!!!!!
- Reset signal seem not to be necessary for read
- The waveforms for reading in the manual shows a reset upfront!!!!!!!!!!
- Behavior between Quartus 15.1 and Quartus 17.1 is different but manual does not show any difference!
- Maybe even Quartus 18.1 behavior is different but there is no new document for that!
Best regards,
Erich

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