Honored Contributor II
10-11-2014 12:01 AM
When running simulations using the Cyclone V DDR2 HMC UNIPHY simulation model I noticed something very strange.If I set the CAS latency to 7, data is written correctly. If I reconfigure HMC to CASL=5, the HMC will drive the DRAM with CASL=5 timing, however it will still set the SDRAM mode register to CASL=7. So the data latched into the SDRAM will be wrong. Anybody have a clue?