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Altera_Forum
Honored Contributor I
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CAS Latency on Cyclone V DDR2 Hard Memory Controller

When running simulations using the Cyclone V DDR2 HMC UNIPHY simulation model I noticed something very strange. 

 

If I set the CAS latency to 7, data is written correctly. 

 

If I reconfigure HMC to CASL=5, the HMC will drive the DRAM with CASL=5 timing, however it will still set the SDRAM mode register to CASL=7. So the data latched into the SDRAM will be wrong. 

 

Anybody have a clue?
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