CVI and vid_datavalid at separate syncs

[Altera_Forum]

Hi to all of you, 

 I#m trying to bring up a self-made board. I have an Cyclone IV E.   The FPGA is used only for Chroma Resampling from 4:4:4 to 4:2:2. At the moment I try to use an TestPattern-Generator and a VCO, thix block is connesctet to a Block with Input-->FrameBuffer-->FIFO--> Output.   The TPG-Block and the Input are with separate wires, the Output from the Frame-Buffer-Block is with embedded Signals. This worked fine when I cannect the vid_datavali-Siganl from the TPG-Block with the vid_datavalid from the Input. BUT in my design I don't have a datavalidsignal or something like this. I know, when I use embedded Signals at my Input I can tie the datavali to Vcc but I need to use separate wires. :)   Does anybody have an Idea how I can solve the Problem? How can I genarate a stabile datavalid-Signal for my Input. I think I have to toggle the Signal on the frame. But I have different frames and I need to use it with all SDI frames (1080i, 1080p, 720i...).   I hope you can help me.   Anja

[Altera_Forum]

Hy Anja, 

 Try this: data_valid <= '0' when ((H = '1') or (V = '1')) else '1';

[Altera_Forum]

Hi, 

thanks for your reply.   I put a NOR-Logic inside, and it works fine for progressive Signals but not for interlace Signals.  Any Ideas for interlace Signals?   Thanks Anja

[Altera_Forum]

Hi to all, I got a working solution which maybe is interessting for somebody. 

 I selectet the incoming Video Data-Siganls and put it on an OR-Logic the I putvthe Output of the OR-Logic to the vid_datavalid input. It works for all Signals, because I have only a Signal if one of the datasignals is available.