FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

CVO II and genlock

Altera_Forum
Honored Contributor II
966 Views

I have a video processor design built using the VIP suite and everything is working as expected using a free-running CVO clock. However, my attempts to genlock the CVO to an external pll do not seem to be working. 

 

I'm using the CVO II module and I have enabled the "Accept Synchronization Outputs" parameter in the qsys GUI. The CVO clock is derived from an external PLL and the PLL also provides a top of frame (TOF) signal which I have attached to the CVO SOF input and the CVO SOF_LOCKED input has been tied high. I have written 0x0019 to the CVO control register (Go bit, Enable Sync Output, Enable Frame Lock). 

 

The CVO generates valid video but I do not see any attempt to align the output frame with the SOF input signal. The Status register reads 0x0005 - the frame locked bit never changes. 

 

What am I missing here? 

 

Michael
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
164 Views

If at all possible I would suggest trying to use the CVO I instead of CVO II. The original CVO has been used with genlock in a couple of working Altera reference designs, but this hasn't been demonstrated for the CVO II yet.

Altera_Forum
Honored Contributor II
164 Views

This is the official response from Altera as well (via SR). The CVI II and CVO II do not currently support Genlock in spite of what the VIP Suite User's Guide says. We have already discovered that embedded syncs don't work for the CVO II (and haven't for several releases of Quartus). The new VIP modules do not appear to be ready for the broadcast video customer. 

 

Michael
Reply