Hello everyone,I am trying to figure out how much latency for a certain configuration of the HIP PCIe MegaCore I can expect on both the transmitter and receiver path of an endpoint device. The reason for this is to determine whether the Hard PCIe IP + internal PHY or the Soft PCIe IP + external PHY provides the solution with the least amount of latency. According to Solution ID 'rd12072009_347' from the Altera Knowledge Base it should be possible to obtain the answer from a simulation. I currently have the simulation up and running in modelsim-altera which uses the auto generated 'pcie_core_example_chaining' project. I have disabled the DMA functionality and the BFM driver now simply generates some basic read memory procedures. I understand most of the Avalon-ST signals which provide me information about the application layer of the IP implementation. I can see when the read request is received and when the read completion is send back. I however do not understand exactly what signals of the remaining layers the IP provides and how I can use these to determine the actual latency. The rx_in and tx_out signals of the core seem to toggle continuously in the simulation so it is not possible for me to see when a transaction starts/stops on the serial PCIe lines. I appreciate any help or guidance. Thank you in advance.
Hi,I am also interested in this question. I also tested the auto generated 'pcie_core_example_chaining' model in ModelSim, the signals tx_st_data and rx_st_data are changed, but the signals tx_out and rx_in don't change. How can I measured the latency on the PCIe HIP?