FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5875 Discussions

Video IP, multi-tap stream

Honored Contributor I



I have a camera with CameraLink interface whose clock run at 82MHz. In the desired configuration, it should supply 10 monocrhome 8-bit pixels of a line per clock tick when the line is active. 


It'd be nice if I could convert the stream from the camera into Avalon-ST Video protocol so that I could use Altera Video components for video processing.  


Can Video cores work with such stream? Is there any ready made core which can bridge such stream into Avalon-ST Video? I haven't read the "Avalon-ST Video Protocol" in chapter 2 in ug_vip.pdf entirely yet. I'm wondering if it's worth it. 


Flattening the original stream into 8-bit stream sounds challenging. I think I'd have to have two, front and back, 80-bit registers and two clock domains. First clock domain would be for frame grabber working with back buffer running at 82MHz. Second clock domain would be for Video cores starting with a sequential circuit that'd turn the front register into stream of 10 video packets and then swap the registers. That is, the second clock domain would have to run at 820MHz which seems like close to or above the limit of PLL on Cyclone IV and I'm not even considering the overhead like the Avalon-ST backpressure. 


Thank you.
0 Kudos
1 Reply
Honored Contributor I

Hi woky. 

Most of VIP modules able to process 4 pixels in parallel, so you can run second clock domain at 820/4 = 205Mhz. It is much closer to be true, but in my opinion it is still very fast for Cyclone IV. I'm using 150 Mhz for video path on Cyclone V 



Sergey Burenkov