CVO and PAL - How?

[Altera_Forum]

Hi all, 

 I am trying to generate a PAL video output using the VIP suite.   At the moment my device (A cyclone 2c35) only has the test pattern generator and the clocked video output.   I have to use seperate sync signals to drive my DAC (its the same as used on the lancelot board) and no matter what I do I can't get a decent signal out. It keeps 'losing' half the vsync pulses.   Firstly I have set the test pattern generator to generate 720x576 interlace. I assume this is correct for PAL? the documentation is a bit poor when it comes to interlace so I'm not sure if this is supposed to be set to 576 or 288?? Also is there any way to change the pattern beyond bars or a plain colour? - both are pretty useless when you are trying to fix vsync problems! :)     Secondly I have set the CVO to the 'PAL' preset with seperate sync wires turned on. Now I can understand how to set 'Horizontal sync' etc. which are helpfully set to zero ;) (these are derived from the 13.5Mhz pixel clock I feed the IP) but I simply can't get my head around how the "active picture line" "F rising/falling edge line" and "vertical blanking rising edge line" are interrelated - it seems random.   No matter how I fiddle with these settings I can't get a nice 50Hz interlace signal out. I always end up with half the vsync pulses missing (even though the F signal toggles) or fields which are nowhere near 50Hz. The active picture line is only correct for the very first field so this is telling me that *somthing* is wrong like I'm feeding it with active video fields that are too big and its spilling over into the next field. Its almost like its trying to generate a 60Hz output.... If I try changing the active picture line or other F edge parameters it typically kills Vsync totally.     So can anyone out there tell me some settings to generate a 720x576i output from the CVO? My current settings are as follows (with a 13.5Mhz pixel clock and a 100MHz 'system' clock driving the IP )   Preset conversion: PAL Image width: 720 Image height: 576 Bits per pixel per colour plane:8 Number of planes: 3 Colour plane transmission format: Parrallel Interlaced video box: Ticked (on)   Pixel fifo size: 720 Fifo level at which to start output: 719 Video in out use same clock? : NO Use control port?: NO   Sync signals: on seperate wires Active picture line: 23 (I am using V9.1 sp2 IP so this box works)   Field 1 parameters:   Horizontal sync: 63pixels (63 x 74nS = ~4.7uS) H front porch: 22 pixels (~1.6uS) H back porch: 76 pixels (~5.6uS) Vertical sync: 5 lines Vertical front porch:6 lines Vertical back porch: 5 lines     Field 0 parameters:   F rising edge line: 313 F falling edge line: 1 Vertical blanking edge line: 311 Vertical sync: 5 lines Vertical front porch: 5 lines Vertical back porch: 4 lines   But this gives me an output missing half its vsync pulses!   Any suggestions most welcome!   Cheers, Tom

[Altera_Forum]

shouldn't the PAL preset set all of the parameters to the appropriate values for that standard?

[Altera_Forum]

It does indeed when you have embedded sync selected - thats easy to do ;) 

 But with seperate syncs its all a bit 'analog' and dependent on your pixel clock, so I think thats why the boxes are left blank.   An example would be nice however, because some of my values/understanding of it must be wrong :)

[Altera_Forum]

Are you trying to do a true composite PAL signal? For that you need more than a simple video DAC. Or are you just trying to do an RGB or YPbPr component output at 576i? 

 In either case, your timings seem a bit off. For a 576i signal with a pixel clock of 13.5 MHz, the usual total frame size is usually 864x625 (864 * 625 * 25 = 13.5M).  One thing to check is if your DAC supports a pixel clock as low as 13.5 MHz. I have seen video encoders which require at least 27 MHz.

[Altera_Forum]

No, I'm not trying to generate composite with colour burst etc.  

 But yes you are correct, I am doing a component RGB output using a DAC (as on the lancelot board) and generating the composite sync using a XOR - This works fine in my application via a SCART connector. I am 100% sure the DAC circuit etc. is correct because its an existing product board (I am trying to replace our 'home spun' graphics circuitry with fancy new Altera IP)      So 864 pixels is the whole line at 13.5Mhz? OK so if my active picture line is 720 pixels that leaves me 144 pixels for Hsync and the front and back porches...   So at say 74nS (13.5Mhz) per pixel clock:    We have to have 4.7uS for Hsync - Thats 63.51 pixels - lets call it 63. leaves 144 - 63 = 81 pixels.   Front porch has to be 1.65uS - Thats 22.29 pixels - lets call it 22. leaves 81 - 22 = 59 pixels.   This means the back porch will be 59 pixels or only 4.36uS.    Using these figures I get Vsync for both fields! - sadly at 51.57Hz. My Hsync measures as 4.64uS Which is OK My front porch measures as 1.2uS and Back porch 4.96uS which are not quite what I was expecting but thats tweakable.   The biggest problem is active video still starting to early - around lines 7 or 8 ish.. My graphics are going to be too high up the screen..   I have attached some pics for your viewing pleasure - thanks for the comments so far - any more are most welcome!

[Altera_Forum]

The CEA861 specs for digital video for 720x576i are as follows: 

 H Sync - 63 Front Porch - 12 Back Porch - 69  Field 1: V Sync - 3 Front Porch - 2 Back Porch - 19  Field 2: V Sync - 3 Front Porch - 2.5 Back Porch - 19.5  This gives a total frame size of:  (12 + 63 + 69 + 720) x (2 + 3 + 19 + 288 + 2.5 + 3 + 19.5 + 288) = 864 x 625  I am not sure how that translates to analog video timings. I am also not sure how the VIP CVO block handles the half line or if it even can. You can't seem to enter half lines into the wizard. The half lines in interlaced video always confuse me a bit. So far I have never tried to use the CVO with interlaced video.

[Altera_Forum]

Kevin - you are a star :) 

 Those values give me a nice 50Hz sync with the video starting correctly!   I see the reason why I have been going wrong. It is with the Vsync front/back porch - I thought this just defined the '6,5,5 & 5,5,4' equalisation pulses, but It appears it has a big influence over the frame timing.   The IP does not 'do' half lines so I just rounded the half lines - my field 0 vertical front porch is set to 3 and back porch to 19.   So for anyone needing the values - here is what I am now using:   (If anyone else uses these values, check they are correct for you, I have not measured all the timing yet)   --------------------------------- Pixel clock @ 13.5Mhz, 720x576i PAL Seperate syncs 24bit RGB in and out:   Preset conversion: PAL Image width: 720 Image height: 576 Bits per pixel per colour plane:8 Number of planes: 3 Colour plane transmission format: Parrallel Interlaced video box: Ticked (on)   Pixel fifo size: 720 Fifo level at which to start output: 719 Video in out use same clock? : NO Use control port?: NO   Sync signals: on seperate wires Active picture line: 23 (I am using V9.1 sp2 IP so this box works)   Field 1 parameters:   Horizontal sync: 63 pixels H front porch: 12 pixels H back porch: 69 pixels Vertical sync: 3 lines Vertical front porch:2 lines Vertical back porch: 19 lines     Field 0 parameters:   F rising edge line: 313 F falling edge line: 312 Vertical blanking edge line: 311 Vertical sync: 3 lines Vertical front porch: 3 lines Vertical back porch: 19 lines     Thanks again Kevin!