CXL ARB/MUX initialization debug

[SJ_Hwang]

Hi,

I am currently implementing the CXL controller using the FPGA. (connected to Intel Xeon Sapphire Rapids Server)

(I am not sure I am writing to the appropriate board. If I need to move this post, please let me know  )

Actually, I am not using the Intel CXL IP and implementing myself based on PCIE IP.

and I am on the road to implement the FPGA that want to be connected to CPU as CXL.io & CXL.cache enabled(CXL type 1 device).

But the problem is I am stuck at ARB/MUX layer initialization flow.

(I already successfully done connecting CPU and FPGA as CXL.io only enabled .

As CXL.io only enabled, ARB/MUX layer is set to bypassed so that ARB/MUX layer initialization flow is not required at this situation. )

In this above picture(Fig. 5-12) from the CXL specification, CPU(Left side) and Endpoint device(Right side) exchange the ALMPs(ARB/MUX link management packets) and finishes the state transition to active state.
but the problem is that CPU is not responding the State_Status_Active_ALMP that notifies the CPU's ARB/MUX layer initialization is done even if previous ALMPs sent well from the endpoint device and received well to CPU.

Can anybody help me with these problems ? 

Any similar circumstances or advices would be welcome

Best,

[WZ2]

Hi SJ,

May I know is the example design of CXL type 1 doesn't work? Why don't use it?

Best regards,

WZ