CXL Type 3 OOO IP AXI issue

[RicardoC]

Hi,

After populating the AFU with custom logic, the AXI interface from the CXL IP seems to have incorrect behavior.

Scenario: standard Avery base testbench attempts to write 1500 CLs to the device. AW channel incoming FIFO has space to hold requests, but W channel is full and cannot take any more data. The custom logic deasserts wready, while maintaining awready asserted, as per spec, but the CXL IP seems to ignore that the awid and awaddress were already sampled, and repeats the same values again once the wready gets reasserted.

In the attached waveform, cursor C1 shows the transaction with awid='h16 getting requested (and accepted by the subordinate), when wready is deasserted. On the next cycle, wready is asserted, but a new AW transaction is issued with the same awid='h16.

The same situation happens a few transactions later, with awid='h1a.

Any comments would be appreciated.

Thank you,

Ricardo.

[JonWay_C_Intel]

Hi @RicardoC This is a bug in 23.2 when OOO is enabled. You can work around this until 23.3 by de-asserting AWREADY and WREADY together if they need to backpressure either the Address or Write data channel.

[RicardoC]

Hi John,

Thank you for the confirmation. We had already worked around the issue in the same manner as you suggested.

Thanks again,

Ricardo.