Intel FPGA Avalon I2C (Host) Core

[jsondergaard]

Does anyone have an example or tutorial on how to use this core on an SoC? I have had success with the Cyclone V using other cores and writing to their registers from the HPS via the Avalon mm to successfully control and operate them. Other than the TFR_CMD register, registers do not retain their value when written to. The register memory maps and their offsets are very clear in the data sheet and I have checked multiple times that I am writing to the correct ones. Any thoughts or areas to check? This has been a pain to figure out. I'm beginning to wonder if I should take the long route and write my own core at this point. Also, as a side thought, is it possible to use the HAL files on the HPS instead of the NIOS II processor? Seems like it would make things much easier. Thank you!

[EBERLAZARE_I_Intel]

Hi,

Can you check this design?

https://fpgacloud.intel.com/devstore/platform/17.1std.1/Standard/i2c-remote-system-update-example/

[jsondergaard]

Eberlazare,

I appreciate the suggestion. This appears to be a different core than the "Intel FPGA Avalon I2C (Host) Core." It is also meant for a MAX 10 dev kit, so the hardware isn't quite the same. I probably should've mentioned that I am using the DE10-Nano from Terasic. With that said, the general Qsys connections I have on my end are relatively the same. 

Thank you, 

Jordan 

[jsondergaard · Accepted solution]

The register addresses in the datasheet actually need to be multiplied by four. Everything is working just fine now. 

[EBERLAZARE_I_Intel]

Hi,

Thanks for the update, glad it worked for you. For Max 10 devices design, you may port it to your device lets say Cyclone V in Quartus.

Your IP doc for ref:

https://www.intel.com/content/www/us/en/docs/programmable/683130/23-1/fpga-i2c-host-core.html

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