FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5884 Discussions

Calculating speed of DDR2-RAM using DDR2-HPC

Honored Contributor II



i've got a question about calculating speed of DDR2-RAM using DDR2-HPC from Altera. 


I'm using CycloneIII-Dev-Board and know, that the maximum theoretical speed of DDR2 is: 

167 MHz * 72 bits * 2 (Both clock edge used) ~= 24Gbps 


Ok, but whats about the DDR2-HPC? How do I calculate it's influence in speed? How fast is this component? 

In the datasheet (http://www.altera.com/literature/hb/external-memory/emi_ddr_ug.pdf) at page 160 they mention, that there is a total read latency of 108ns and a total write latency of 66ns. Does it mean, that one read operation takes 108ns? And then, after waiting 108ns the next read operation could start? This would slow the effective speed of using DDR2 down vastly, wouldn't it? 


Or what did I get wrong? 


Thanks for every hint!
0 Kudos
2 Replies
Honored Contributor II

Yes, it takes 108 nsec before the first word read from DDR2 memory reaches your function. So if you require just one word, and you wait for each access to be finished before requesting the next it will take 108 + 12 nsec , or 8.33 MHz (max.). The idea is that you request either larger transfers (so the read latency gets less important) or if you have shorter requests that you pipeline them early to the HPC controller. The HPC will issue the read commands as early as possible and from the first word returned to the second word you will not see this read latency, but the actual delays between the read command issued to the DDR2 RAM (which could as little as 2 clocks if the next word requested is in the same row and bank as the previous). At some point row/bank switching and refresh will occur, making speed predictions a bit more difficult.

Honored Contributor II

Latency is not the same as efficiency. 


Your commands are pipelined so best case you could get close to 24Gbps but when the DDR2 needs to do a refresh and you're stuck waiting. So the overall speed or efficiency comes down to what read/write ratios and patterns you are using and what addressing patterns you are accessing (sequential or random?). 


Its a fairly complex calculation and I am not sure Altera can provide an exact answer for your system. I'd perhaps look more at a memory vendor for this sort of information.