Can nPERST pins be used as PCIe reset if Intel® Stratix® 10 PCI Express* Hard IP is used as Root Complex?

[Wujun]

Hello,

According to the Pin Connection Guildline, Pin Functions of nPERST[L,R][0:2] are input or I/O. When you do not use this pin as the fundamental reset, you can use this pin as a user I/O pin.

Is it mean when I use this pin as fundamental reset, this pin is input? If I use the PCIe hard IP as PCIe Root Complex, do I need to assign a GPIO as fundamental reset?

[Rahul_S_Intel1]

Hi,

Is it mean when I use this pin as fundamental reset, this pin is input?

>>  Input

 If I use the PCIe hard IP as PCIe Root Complex, do I need to assign a GPIO as fundamental reset? >> NO

Kindly find the explanation

When the PCIe HIP on a side (left or right) is enabled, the nPERST pins on that side cannot be used as general-purpose I/Os (GPIOs). In this case, connect the nPERST pin to the system PCIe nPERST signal to ensure that both ends of the link start link-training at the same time.

[Wujun]

So if I use the PCIe HIP and use S10 as Root Complex (system side), which pin can be connected to the End Point (device side) PERST#?​ Because as a RC, S10 need a output PCIe PERST#, but the S10 nPERST pin is an input signal.

[Rahul_S_Intel1]

Hi ,

Sorry to keep you to wait this much long , I have done my research, kindly find the details.

When the PCIe HIP , setting is made as root port , the pin_perst configured as input , the same I have verified with Stratix 10 example design.

Kind find the attached screen shot for PCIe HIP for your reference which I took from the example design.

[Wujun]

Hi ,

The pin_perst configured as input？

->From the screen shot, pin_perst is just an internal signal, but I need a pin name which can be found in the Intel® Stratix® 10 Device Family Pin Connection Guidelines. Do you mean when S10 is setting as root port, nPERST pin can be used and be configured as output?

[Rahul_S_Intel1]

Hi ,

The pin_perst configured as input ?

>> Yes

From the screen shot, pin_perst is just an internal signal

>> Yes you are right, it is an internal signal . This internal signal pin_perst of each hard IP instance to the corresponding nPERST pin of the device. ( Reference pag no: 48) , also attaching the screen shot also for easy reference.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_s10_pcie_avst.pdf

Do you mean when S10 is setting as root port, nPERST pin can be used and be configured as output?

>> No

[Wujun]

So how to control the PCIe reset? In this case, both Root port and End port are input signals. Connect a FPGA I/O pin with S10 nPERST and End Port PCIe reset?

[Rahul_S_Intel1 · Accepted solution]

Hi ,

I will share you one design , I hope it is publicly available with Root port .

Use the below as reference

Kindly have reference.

https://rocketboards.org/foswiki/Projects/Stratix10PCIeRootPortWithMSI

[Wujun]

Thank you. Refer to the schematic, an I/O is connected to the End Port PCIe reset.

[Rahul_S_Intel1]

Hi,

I have done further analysis on the design , I found the pin connection from the design and sharing for your reference ,

With the below analysis , I am kindly requesting to close the case

[Rahul_S_Intel1]

pin file from the project

[Rahul_S_Intel1]

Hi ,

Kindly let me know if you need further assistance