Can't find clock output pins of DDR

Altera_Forum · ‎08-20-2010

Hi,

I have a NiosII design that contains a ddr_sdram core. When I moved from Quartus 9.0 to 9.1, it started giving me the following error:

Error: DDR Post compile timing analysis failed
Error:  Couldn't find the clock output pins. Stop.

On page 44 and 45 of http://www.altera.com/literature/rn/rn_ip.pdf it states a solution to my problem:

Workaround
Make the following two assignments:
ddr_pll_stratixii:g_stratixpll_ddr_pll_inst Preserve PLL Counter Order On
ddr_pll_stratixii:g_stratixpll_ddr_pll_inst|altpll:altpll_component|_clk3* Global Signal Global Clock
Replace the file names of the PLL with those in your DDR SDRAM controller design.

Where/How do I make the two assignments? and Where/How do I replace the file names?

I think I am having a brain fart.

Thanks,

-Ben

Altera_Forum · ‎08-24-2010

make the assignments in the assignment editor.

The fitter report should provide a name for your actual PLL instance.