FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5986 Discussions

Can we separate the inout data bus PFL (parallel flash loader) IP core?

Altera_Forum
Honored Contributor II
822 Views

Hi, 

 

we are using the PFL ip core in MAX2 cpld to download the FPGA configuration file to flash and to program the ARRIA2 FPGA. 

 

we had a requirement to dowload the configuration file from FPGA in the production without using JTAG.For this we are having the flash programming in FPGA and using SPI interface to CPLD.(we don't have hardware connections from FPGA to FLASH) 

 

we need to multiplex the inout data bus between PFL and user flash programming module. 

 

The PFL core directly gives inout data bus in the entity.Can we split this data bus to seperate input and output data busses in PFL core, so that we can multiplex the inout data bus between two flash control modules? 

 

 

Thank you, 

Regards, 

Ramesh.B
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
94 Views

Why not? You would preferably implement the changes in pfl.vhd, that is already multiplexing between program and configuration function of the core. But if you don't want to touch the core, you can also add a wrapper.

Altera_Forum
Honored Contributor II
94 Views

Thank you for your reply.I edited the PFL core just to split the inout bus into seperate in and out busses and added the wrapper to it. 

 

Regards, 

Ramesh.B
Reply