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Altera_Forum
Honored Contributor I
726 Views

Cannot find SMA output clock in DE4

Hi, 

 

I am trying to adapt an example design for an SFP module that was designed for the Stratix IV GX "development" board into one that would work on the Stratix IV GX "DE4" (the board that I have). 

 

I am confused about the differences in the clock circuitry and PLL capabilities of the two boards. 

 

The PLL part of the code looks like this (it's in the top level entity): 

 

In the module declaration: 

input [1:1] clk_125_p, 

output clkout_sma, 

 

Later in the code: 

pll_sma_out pll_sma_out_inst  

(  

.inclk0 ( clk_125_p[1] ),  

.c0 ( clkout_sma ),  

.locked ( )  

); 

 

In the example design, clkout_sma is mapped to PIN_W33 and clk_125_p[1] to PIN_AF34. 

 

However, I can't find any signal that corresponds to this for the DE4. Is there a way to map this design to work for the DE4? 

 

Also, I am a bit confused about what SMA does. From what I understand the design takes a 125MHz clock and uses it as an input to a PLL. The PLL's output clock is clkout_sma, but where is it used? is it in the HSMC port? 

 

Thank you.
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1 Reply
Altera_Forum
Honored Contributor I
28 Views

The block diagram clock connections of the de4 gives already an overview, how the SMA sockets are connected. But I assume, that schematics are provided with the Kit, you should consult it in case of doubt.