Developed a simulink model by importing VHDL design of FIR compiler II IP. I integrated a vhdl wrapper (to buffer the input data based on sink_valid and sink_ready) import to feed the input to the filter. When I try to compile it gives error message "cannot resolve algebric loop". However, I used the same wrapper for fir compiler(from dsp builder library) based model, it works fine without any error.Can somebody help in this regard. Thanks.
Unless someone has experienced this exact error, it's probably best if you submit a support request to Altera.They will need your setup for both the working and failing designs to reproduce the issue, and will probably ask if you are running the latest version of the quartus tools. So if you can provide that with your support request information, it may save at least a few days of back and forth. I also recommend if you have a local Altera FAE, you ask them, and have them help you bird-dog the issue through the support process. Pete
Can you pls tell me how to submit this issue to Altera support online? I tried to go to "mySupport" then "Get Design & Support resources" then "mysupport" to create an service request. But it is not working out.
Your design in Simulink contains a loop with no delays. (At least no delays Simulink can see since it can't actually see into your HDL Import block).Presumably you've connected the sink_ready output to some logic which then drives sink_valid and sink_data. You could resolve this by inserting a delay block on your ready path. The specifics of doing that may be quite tricky but should be possible.